HomeProjectsPeoplePublicatons
Search:
   
 

BWRC Publications

• Pubs Top
• Search
• Add a pub

Quick search by...
Year: 
Retreat: 

Log in.
Understanding DC Behavior, Voltage Limits and Related Design Issues in Sub-threshold CMOS Logic
Massimo Alioto

Citation
Massimo Alioto. "Understanding DC Behavior, Voltage Limits and Related Design Issues in Sub-threshold CMOS Logic". University of Siena (Italy), October, 16, 2009.

Abstract
In the last years, sub-threshold CMOS logic circuits have become very popular in ultra-low power applications. Designing at such ultra-low voltages (a few hundreds of mV) is challenging and requires a deep understanding of the circuit robustness and the underlying design tradeoffs, which are dramatically impacted by PVT variations. For the first time, this seminar deals with the DC behavior of sub-threshold CMOS logic gates, deriving general and closed-form expressions for fundamental parameters (e.g., small-signal gain, noise margin, …). To this aim, general and simple circuit models of MOS transistors in sub-threshold are introduced. The analysis permits to gain an insight into the degradation of the DC characteristics at ultra low voltages, and evaluate the minimum supply voltage that enables correct operation. Results are organized into a framework that permits to easily include the impact of PVT variations on the noise immunity and the voltage lower bound. Examples in a 65-nm technology are presented.

Electronic downloads

Citation formats  

  • HTML
    Massimo Alioto. <a
    href="http://infopad.eecs.berkeley.edu/php/pubs/pubs.php/1145.html"><i>Understanding
    DC Behavior, Voltage Limits and Related Design Issues in
    Sub-threshold CMOS Logic</i></a>, University of
    Siena (Italy), October, 16, 2009.
  • Plain text
    Massimo Alioto. "Understanding DC Behavior, Voltage Limits
    and Related Design Issues in Sub-threshold CMOS Logic".
    University of Siena (Italy), October, 16, 2009.
  • BibTeX
    @seminar{Alioto2009,
        author = {Massimo Alioto},
        title = {Understanding DC Behavior, Voltage Limits and
                  Related Design Issues in Sub-threshold CMOS Logic},
        organization = {University of Siena (Italy)},
        month = {October},
        day = {16},
        year = {2009},
        URL = {http:///php/pubs/pubs.php/1145.html}
    }
    

Posted by Olivia Nolan on Oct 20, 2009..

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.