Design and Implementation of Digital Timing Recovery and Carrier Synchronization for High Speed Wireless Communication

Paul James Husted,  2000, M.S. (advisor: Bob Brodersen)

As communication algorithms continue to increase in complexity, greater constraints are placed upon the hardware used to fully utilize the capabilities of these algorithms.  These new algorithms attempt to achieve the highest possible bandwidth efficiency by utilizing diversity in time, frequency and space dimensions, leaving little room for error in synchronization systems.  Furthermore, as more high bandwidth receivers become incorporated into small mobile devices, this high synchronizer performance must be attained at a low power cost as well.   The driver for this project is the design of an indoor wireless communication system capable of high data rate downlink and multiple portable receivers.  We will implement and test advanced timing recovery and carrier synchronization methods that move most of the co9mputation to the digital back end, reducing power consumption.