FOR RELEASE:
October 15, 1998

For North America Distribution

      Motorola Debuts New M-CORE(tm) M300 Processor Family
   With Floating Point Unit and Enhanced Core Performance
                for Numeric Acceleration  

   Provides higher calculation rates at lower power levels

AUSTIN, Texas -- October 15, 1998 -- Optimized for numeric acceleration,
higher core performance, and superior code density which provides higher
calculation rates at lower power levels,  Motorola today unveiled its M300
M-CORE(tm) microprocessor at the Microprocessor Forum hosted by MicroDesign
Resources.  Targeted at higher performing systems, the M300 core retains the
superior code density and low-power design of the original M-CORE architecture.
Boasting a 1.4X performance improvement on the already efficient M200 family,
the M300 achieves even more work in fewer clock cycles at lower frequencies. 
Compared to other RISC processors running at much higher frequencies, the
M300's ability to work at lower frequencies while accomplishing the same task
in a comparable amount of time adds additional power savings to
power-conscious applications.  The first M300 family implementation will be in
Motorola's 0.22 um process technology and operate from DC - 100MHz at 2Volts. 
The M300 will be available in products Q1 '99.    
"We see competitors continuing to move to speeds of 100MHz and beyond to
increase their performance, which doesn't always makes sense for
battery-powered solutions," stated Jim Thomas, vice president and director of
the M-CORE Technology Center.  "We took an overall system approach to
performance that allows customers to save power while providing the similar
performance at a lower frequency and cost." 

Optimized for numeric/math intensive applications, the M300's Floating Point
Unit affords numeric acceleration critical for applications with low power and
price sensitive demands.  Portable games, DVD players, camcorders, as well as
engine control and servo-motor control applications, will benefit from the
addition enhanced numeric performance.  Furthermore, while addressing the
customer's needs for higher performance, the M300 also incorporates new
additions to the M-CORE architecture that allow future growth of the core
without depleting architectural headroom.

"The M300 represents the next step in M-CORE performance for our customers
desiring numeric acceleration," said C.D. Tam, corporate vice president and
general manager of the Transportation Systems Group.  "The M300 continues to
represent the excellence in low power, high temperature design that the M200
introduced, thus raising the performance level for customers requiring
improved math performance for industrial applications."

32-bit Dual Instruction Pre-fetching

The addition of a 32-bit Dual Instruction Pre-fetching feature speeds the
ability of the M300 to load instructions into the core.  The M200 family of
the M-CORE architecture applies 16-bit instructions while utilizing a 32-bit
internal data path.  The M300 now fully employs the entire data path to grab
two 16-bit instructions inside the machine with a single instruction fetch. 
The M300 can store up to four instructions in an internal two level buffer
that is then used to directly supply the instruction register on demand.  The
M300 queues instructions in the instruction register where they can be
immediately decoded and dispatched to the execution units.  This approach
enables the internal register to remain full without having to wait to bring
in single 16-bit instructions one at a time.  This reduces the overall Bus
bandwidth necessary to fetch the instruction stream, affording
alternate/multiple Bus Masters more opportunity to utilize the shared Bus. 

Instruction Pipelining

The M300 also utilizes instruction pipelining, allowing non-dependent
Load/Store instructions to execute in parallel.  The M-CORE architecture
Load/Store instructions require two cycles of execution; one for effective
address calculation and one to perform the memory access.  New logic
implemented in the M300 family performs data dependency checking for
sequential Load/Store instructions, permitting execution of non- dependent
instructions to occur in parallel reducing the number of cycles required for execution.

Low-Cost Branch Folding
Another performance-related feature of the M300 family is low-cost branch
folding.  Typically, a branch instruction takes two clocks to execute; one to
fetch and one to calculate the loop address.  The M300 takes a simpler
approach that realizes significant performance improvement over the M200 while
maintaining the overall goal of low power. 
The M300 performs detection and utilization of short backward branch
instructions.  Upon detection, three savings are identified; the address of
the branch, the branch target address, and the fall-through instruction.  The
advantage being, once detected and saved, upon each pass through the loop, the
branch instruction is replaced with the instruction pointed to by the loop
address.  Two cycles of execution are saved for each pass through the loop,
reducing the overall number of execution cycles.  This yields a seven-to-eight
percent improvement in performance over the M200 without adding complexity to
the design.

The M330 Core Adds Numeric Acceleration

The first implementation of the M300 family is the M330 core.  Several
additional numeric acceleration features including a Single Precision Floating
Point Unit were
added to the M330.  The Floating Point has several new Instruction Set
Additions including:

   add, subtract, multiply, int, float          2 clocks
   divide                                      17 clocks
   mult acc, mult sub                           3 clocks
   negate, cmplt, cmpne                         1 clock

Floating Point instructions can operate in two Real-Time Execution Modes;
Default Results or IEEE Compliance through Software Handling.  Also
implemented is a Fast Integer Multiplier, which realizes 16 x 16
multiplication in a single clock and 32 x 32 multiplication in two clock
cycles.  Additional hardware was added to speed up the existing (mult)
instruction that appeared in the M200 core family.

About M-CORE

Quickly recognized by the embedded market as an innovative solution since its
October, 1997 introduction, Motorola's ultra-low power, micro-RISC M-CORE
architecture boasts a multitude of design wins in the demand-driven
electronics, portable, consumer, wireless, industrial, and transportation
markets.  The M-CORE technology combines Motorola's unparalleled technical
RISC experience with its vast expertise in control-oriented applications. 
Designed with optimized growth in mind; the core's inherent design features
and best-of-class development tools deliver a cutting-edge solution ideal for
a wide range of highly integrated, low-power embedded computing applications
where memory efficiency, time-to-market, and system cost are critical.

About Motorola

As the world's #1 producer of embedded processors, Motorola's Semiconductor
Products Sector offers multiple DigitalDNA(tm) solutions which enable its
customers in the consumer, networking and computing, transportation, and
wireless communications markets, to create new business opportunities.
Motorola's semiconductor sales were US$8.0 billion in l997.  

Motorola is a global leader in advanced electronic systems and services.  It
creates software-driven products that provide integrated customer solutions
and Internet access via wireless and satellite communications, as well as
computing, networking, and automotive electronics.  Motorola also liberates
the power of technology by providing essential digital building blocks in the
form of embedded semiconductors, controls and systems. Sales in 1997 were
$29.8 billion.

                            #  #  #

Motorola is a registered trademark and DigitalDNA is a trademark of Motorola,
Inc.  M-CORE is a trademark of Motorola, Inc. All other tradenames, trademarks
and registered trademarks are the property of their respective owners.

©Copyright 1994,1997 Motorola, Inc. All rights reserved.